Parity Check Gates in Tunable Coupled Superconducting Circuits

As Quantum computers move closer to requiring error correction the need to optimize the underlying parity checks that drive Quantum Error Correction becomes ever clearer. Parity checks on well-known codes such as the surface code require multiple CNOT gates each on different qubits. Reducing the number of two qubit gates for these parity checks would reduce the overall operation time for surface code rounds and reduce the error rate of systems with multiple parity checks in.

 

The Tunable coupler architecture has emerged as the most promising architecture or superconducting quantum computers, within the architecture it’s possible to engineer large enough ZZ interactions which can perform multi qubit parity checks in a single shot measurement. Here we report on progress made towards the measurement of multi qubit parity checks within a system with tunable couplers. Within this project we aim to perform and benchmark these gates, testing their performance and comparing them to the standard multi CNOT gate decomposition.