Device-to-algorithm simulation of silicon spin-qubit arrays

Semiconductor spin qubits in gate‑defined quantum dots pair long coherence with CMOS‑compatible fabrication, making them attractive for scalable processors. Operating even modest arrays demands a coupled, nonlinear description that captures device electrostatics (cross‑capacitance, charge screening) and multi‑electron interactions. We introduce QuDiPy (Quantum Dots in Python), a general‑purpose, layout‑aware simulator for electron spin qubits in silicon that links device geometry and voltages to qubit‑level dynamics across diverse architectures, including node‑network designs [1]. From user‑specified gate layouts, QuDiPy builds a voltage‑tunable Hubbard model, derives spin‑Hamiltonian parameters (Stark shifted g-factors, exchange couplings), synthesizes control pulses for a universal gate set, and simulates open‑system dynamics under realistic noise. We use QuDiPy to identify robust operating windows and to quantify how voltage noise and electrostatic disorder affect algorithmic fidelities in small processors. This end‑to‑end workflow informs device design and control co‑optimization, providing a reproducible path from layout to algorithm‑level performance.

1. B. Buonacorsi et al, Quantum Sci. Technol. 4, 025003 (2019).