Bit Error Correction Through CMOS Circuit Coupling: A Tensor Network Approach

Logical bits implemented with CMOS technology, like all physical bits, are subject to thermal noise that can stochastically trigger unintended bit-flip errors. Traditionally, these errors are suppressed by increasing the gain voltage, but miniaturization and in-vivo computing impose low voltage limits on circuit design. Our work focuses on an alternative strategy to optimize the accuracy-dissipation balance when the gain voltage cannot simply be increased: by building multiple error-prone CMOS units into a larger bistable system that encodes a single logical bit. We push a previously established stochastic master equation model for a CMOS circuit to larger, more complex circuits. Here, we combine a judicious basis set expansion with tensor network methods to numerically solve for the steady-state thermodynamics (dissipation rate) and the relaxation timescales (error rate) for bistable coupled circuits. We establish tensor network methods to significantly advance numerical analysis of stochastic circuit models capable of faithfully resolving both rare events and thermodynamics. Equipped with this methodology, we compute the benefits to accuracy that can be achieved by chaining together units, which imposes a natural error correction through inter-unit correlations.