Full characterization of a logical qubit in a trapped ion quantum computer

Understanding the performance of logical qubits will be critical to developing utility-scale quantum computing. Most existing research has concentrated on characterizing the logical idle, or quantum error correction cycle, often through memory experiments. Here, we employ gate set tomography (GST) to probe the performance of a complete logical gate set encoded in the Steane [[7,1,3]] code—including both transversal and non-transversal gates—on one of Quantinuum’s trapped ion processors. We evaluate how well the GST estimates fit the data, addressing the fundamental question of whether logical qubit dynamics are well-described as Markovian processes. Further, we explore to what extent quantum error correction tailers noise. Finally, we investigate what insights the syndrome data generated by logical characterization experiments can provide and consider how such data might be used in conjunction with more standard characterization methods to assess the performance of higher-distance codes.