Encoded random access quantum memories (Part 2/2)

Random Access Memories (RAM) are indispensable to classical computing but remain notably absent in superconducting qubit architectures. Achieving scalable quantum computation requires dedicated, integrated quantum memory to work in parallel with a quantum error-corrected processor. We present an integrated architecture [1] that combines processors with quantum memories, of which we experimentally realized a unit cell for superconducting qubits [2]. Our device includes a storage cavity layer containing high-coherence memory registers (implemented using 3D multimode cavities), managed by a processor cavity and transmon layers.

In this work, we demonstrate progress toward applying bosonic quantum error correction to extend the lifetime of our storage modes. Specifically, we implement a protocol that sequentially swaps the state of selected storage modes to the processor cavity, where a transmon ancilla mediates syndrome extraction and active correction cycles. Our error correction protocol is the crucial ingredient that enables scaling random access memories past the constraint of finite coherence, thereby unlocking the architecture's full potential for enhanced control and capacity.