Unified Control Architecture For Spin Qubits in Quantum Dot Devices

Operation of spin qubits in gate-defined quantum dots requires tightly synchronized control across DC biasing, RF excitation, and lock-in measurement channels. Conventional experimental setups rely on multiple stand-alone instruments for these components, which are costly and suffer from high communication overhead and latency due to inter-instrument triggers and software reconfiguration. Existing open-source RFSoC-based controllers offer partial solutions but remain limited by large on-chip memory demands for long adiabatic chirp pulses—often hundreds of microseconds—and by passive signal-generation architectures that require host-side procedural programming. We present a unified FPGA-based control architecture that integrates all three components—DC, RF, and lock-in—on a single ZCU216 RFSoC platform. Our design supports 24 DC DACs, 12 RF I/Q channels, and 2 RF DAC/ADC pairs operating fully in parallel with deterministic, cycle-to-cycle synchronization. Instead of traditional “store-and-play” waveform buffers, signal generation is defined at a high level through composable instructions that specify pulse segments, delays, and iterations. Once launched, all channels autonomously execute these instructions in lockstep, enabling complex measurement sequences without software latency. To accommodate long adiabatic pulses and arbitrary phase modulation, we introduce a zero-memory parabolic-counter + CORDIC solution that dynamically synthesizes second-order sinusoidal waveforms with tunable instantaneous frequency and phase. This architecture provides a scalable, low-latency, and fully parallel control framework for semiconductor spin-qubit experiments.