Developing High-Performance Superconducting Quantum Hardware

Superconducting quantum computing is rapidly progressing toward fault tolerance by pursuing a roadmap focused on simultaneously increasing performance and scale. This talk details advancements in next-generation architectures, demonstrating the capability to achieve below-threshold Quantum Error Correction (QEC) and significant logical error rate suppression. These substantial performance gains are enabled by systematic integration testing coupled with modeling and error budgeting to identify logical performance limitations, resulting in crucial improvements in qubit coherence, operational fidelities, and the reduction of correlated error mechanisms. We will also discuss a suite of approaches to mitigating scaling challenges, e.g. utilizing automated software optimization to counter device imperfections and advanced material and device engineering to suppress system-level noise. These integrated hardware and control strategies provide the essential foundation for building and operating reliable, error-corrected quantum computers.