Lattice surgery in near term experimental planar architectures

Building a scalable, fault-tolerantly error-corrected quantum computer requires implementing a fault-tolerant universal gate set. For experimental platforms with planar layouts and limited qubit connectivity, the surface code—augmented by lattice surgery—is a leading approach. Motivated by superconducting-qubit experiments, we present detailed simulations of surface-code lattice-surgery protocols in new experimentally relevant settings. We report optimizations of lattice surgery through general overhead reductions and the use of in-sequence logic. Furthermore, we compare lattice surgery based on stabilizer measurements in standard four-valent and alternative trivalent qubit connectivity architectures, finding improved logical error rates for the latter. Finally, we study lattice surgery between surface-code patches separated by a linking region and analyze how the size and relative noise strength of this region influence the correctability of the logical encoding.