VIO, an architecture for scaling superconducting quantum processors - Part 1: introducing the architecture

Scaling quantum processors to the million-qubit regime is fundamentally constrained by the I/O density and fan-out limitations of planar architectures. We present VIO, a 3D architecture designed to overcome these scaling barriers. VIO employs a novel 90-degree packaging technique that connects the horizontal qubit plane to a vertical chipstack. This stack, composed of micromachined silicon substrates and superconducting circuits, provides dense, low-loss interconnects compatible with high-density flexible cabling.

We present key features of the VIO architecture, paving the way to 10k- and later million qubit systems: the co-integration of passive and active components (e.g., filters, parametric amplifiers) directly into the vertical stack, which minimizes signal loss, reduces routing complexity, and meets stringent cross-talk requirements; modular scaling by tiling quantum modules via low-loss chiplet-to-chiplet interconnects; and compatibility with chiplets of all superconducting qubit modalities.