VIO, an architecture for scaling superconducting quantum processors - Part 2: experimental results

We report on the experimental validation of the foundational technological elements of the VIO architecture, a 3D architecture designed to overcome scaling barriers in superconducting quantum processors. We present experimental data from a stack of vertical input/output chips interfaced with a horizontal chip via horizontal-to-vertical connections. Signal integrity of the vertical stack as a signal input/output solution for qubit planes has been characterised, demonstrating high-fidelity signal transmission and low crosstalk. Furthermore, we discuss advancements in modular chiplet-to-chiplet connections and the development of readout components to be integrated within the VIO stack.