Cryogenic BiCMOS chiplets for large scale high-fidelity readout of co-packaged exchange-only qubits

High fidelity readout of large-scale silicon quantum processors requires high signal to noise ratio (SNR) determined by target fidelity, low integration time determined by qubit relaxation and low power dissipation limited by cooling capacity of dilution refrigerators.

Targeting a 99.9% readout fidelity within 500 nanoseconds integration time, this work presents a system architecture for large scale single electron transistor (SET) readout employing (1) a multi-channel co-packaged low noise amplifier (LNA) integrated circuit (IC) dissipating 1.5 uW/channel at 100 millikelvin stage; (2) a multi-channel transimpedance amplifier (TIA) IC dissipating 1.5 mW/channel at 4 Kelvin stage and (3) lock-in signal generation/demodulation at 300 Kelvin.