Cryogenic chip packaging with TSV interconnects for scalable spin qubit control
POSTER
Abstract
To realize large-scale silicon quantum computers, it is essential to develop an advanced packaging platform capable of integrating a large number of qubits. In silicon spin qubit systems employing electric dipole spin resonance (EDSR), high-frequency control signals in the order of 10 GHz are required. To deliver these signals while maintaining signal integrity, vertical interconnects are indispensable, replacing conventional wire-bond connections.
In this work, an active silicon interposer with via-last through-silicon vias (TSVs) was developed, and the signal transmission characteristics of TSV pairs were evaluated from DC to 20 GHz under cryogenic conditions. The interposer was fabricated using a standard 180 nm CMOS process and integrates signal switching circuits, while embedding TSVs directly beneath peripheral pads. Qubit chips are mounted face-down in a flip-chip bonding, preserving their as-fabricated orientation. TSVs have an aspect ratio of 3, with a 40 μm diameter and 120 μm depth (equal to the interposer thickness), ensuring both mechanical robustness and reliable formation. The TSVs were filled with Cu and used TiN as a barrier layer.
This architecture eliminates wire bonding and provides a multifunctional, scalable platform for multi-qubit integration. The feasibility of TSV-based signal transmission for qubit applications was confirmed by measuring scattering parameters from DC to 20 GHz under cryogenic conditions.
Ref.
[1] K.J Chui, et al., IEEE ECTC2023.
In this work, an active silicon interposer with via-last through-silicon vias (TSVs) was developed, and the signal transmission characteristics of TSV pairs were evaluated from DC to 20 GHz under cryogenic conditions. The interposer was fabricated using a standard 180 nm CMOS process and integrates signal switching circuits, while embedding TSVs directly beneath peripheral pads. Qubit chips are mounted face-down in a flip-chip bonding, preserving their as-fabricated orientation. TSVs have an aspect ratio of 3, with a 40 μm diameter and 120 μm depth (equal to the interposer thickness), ensuring both mechanical robustness and reliable formation. The TSVs were filled with Cu and used TiN as a barrier layer.
This architecture eliminates wire bonding and provides a multifunctional, scalable platform for multi-qubit integration. The feasibility of TSV-based signal transmission for qubit applications was confirmed by measuring scattering parameters from DC to 20 GHz under cryogenic conditions.
Ref.
[1] K.J Chui, et al., IEEE ECTC2023.
*This work was supported by JST Moonshot R&D Grant Number JPMJMS226B-6
Presenters
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Misato Taguchi
- Kobe University