General circuit compilation protocol into partially fault-tolerant quantum computing architecture

As we are entering an early-FTQC era, circuit execution protocols with logical qubits and certain error-correcting codes are being discussed. Here, we propose a circuit execution protocol for the space-time efficient analog rotation (STAR) architecture [1]. Gate operations within the STAR architecture is based on lattice surgery with surface codes, but it allows direct execution of continuous gates Rz(θ) as non-Clifford gates instead of T = Rz(π/4). Rz(θ) operations involve creation of resource states |m_θ> = (|0〉+ e^iθ |1〉)/√2 followed by ZZ joint measurements with target logical qubits. While employing Rz(θ) enables more efficient circuit execution, both the creation and the joint measurement are probabilistic processes and adopt repeat-until-success (RUS) protocols which are likely to result in considerable time overhead. Our circuit execution protocol aims to reduce such time overhead by parallel trials of resource state creations and more frequent trials of joint measurements. By employing quadratic unconstrained binary optimization (QUBO) in determining resource state allocations within the space, we successfully make our protocol efficient.

[1] Y. Akahoshi, et al. PRX Quantum, 5, 010337 (2024)