Device Integration and Process Design Kit based on Intel 18A Technology for Scaling Si/SiGe Spin Qubits

This talk will highlight our latest results towards fault tolerant full stack quantum computing based on silicon spin qubits. This includes mapping quantum error correction (QEC) d=2 repetition code onto a 4 qubit processor along with demonstrating extensible 2D qubit arrays with similar behavior to our 1D qubit baseline. We have leveraged our 18A process technology to create a customized process-design-kit (PDK) for scaling up spin qubits and have used it to create 2D spin qubit arrays up to several hundred qubits. This is enabled by a careful co-design across the full stack accounting for QEC topology/ scheduling, system integration, control/signal delivery, advanced packaging, qubit operation, and read out. We will also review our electrical characterization infrastructure, which is based on standard semiconductor industry protocols. This allows us to get quick info turns on qubit quality and yield as well as highlight critical process parameters for device-integration development to meet qubit fidelity targets for fault tolerant operation.