Weight-four parity checks in silicon - don't miss the bus

Recent advances in coherent spin shuttling have made sparse semiconductor spin qubit arrays an appealing solid-state platform to realize quantum processors. The dynamic and long-range

connectivity enabled by shuttling is also essential for many quantum error-correction (QEC) schemes. Here, we realize a silicon spin-qubit array that is connected by a shuttling bus for coherently transporting qubits that can interact at four isolated locations we call bus stops. With direct charge sensing unavailable in most the device, we dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition (QND) spin measurements. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X- and Z-type parity checks up to weight- four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the entanglement of a five-qubit Greenberger-Horne-Zeilinger (GHZ) state, constituting the largest such state ever constructed with gate-defined semiconductor spins. This work opens immediate opportunities to pursue QEC experiments with spin qubits, and the protocols developed here lay the groundwork for the modular calibration and operation of sparse spin qubit arrays. We will close with a summary of related work in our group.