Implementing quantum error correction on spin qubit arrays with shuttling

Spin qubits in silicon quantum dot arrays are a promising quantum computation platform for long-term scalability. In this work, we explore how QEC can be mapped to spin qubit arrays, taking advantage of fast high-fidelity shuttling operations to ease wiring constraints and enable better-than-planar connectivity. We determine the sensitivity of these QEC protocols to gate, readout, idling, and shuttling error rates, specifying achievable targets for future hardware development that will enable scalable, efficient error correction.