Mapping low density parity check codes to quantum charge-coupled devices for algorithmic utility

Quantum error correction protocols provide a means to achieve algorithmic utility with imperfect quantum devices by redundantly encoding logical information across noisy physical resources. Quantum low-density parity check (qLDPC) codes are a leading approach due to their high encoding rates and low overhead logical operations. However, good qLDPC codes require long-range connections. In architectures with spatially fixed qubits, such long range connections are difficult or impossible to implement. In contrast, quantum charge-coupled devices (QCCD) permit long-range transport operations between trapped ion qubits. Furthermore, QCCD architectures have demonstrated the highest recorded single- and two-qubit gate fidelities across existing quantum computing modalities that are well below the thresholds of many interesting qLDPC codes. In this work, we demonstrate the necessary tools and abstractions to map qLDPC protocols to QCCD architectures, which is expected to enable investigations of optimal code designs. We apply this framework to the qLDPC family of generalized bicycle codes, and we perform device level simulations with physically informed noise models. Based on the simulation results, we estimate the capabilities of a device as a function of the number of qubits, which indicates the resources required for useful applications.