Surface code scaling on heavy-hex superconducting quantum processors

Implementing the surface code on QPUs with fixed, non-native connectivity is pivotal for fault tolerance applications, since architecture designs may favor other goals, such as logical-gate compilation, over code performance. We demonstrate surface-code scaling on IBM heavy-hex hardware using a co-designed embedding and control stack. A depth-minimizing fold/unfold schedule of SWAPs with bridge ancillas, combined with gap-aware dynamical decoupling, enables anisotropic scaling on Heron devices from distance 3 to (dx, dz) = (5, 3) and (3, 5). Increasing dz (dx) improves error suppression for Z-basis (X-basis) logical states across 10 cycles spanning 80 microseconds. We introduce an entanglement-fidelity metric derived from X- and Z-basis logical-error data that yields per-cycle, SPAM-aware bounds to quantify experimental performance. Our results show that optimially combining error correction and dynamical decopuling, establishes a concrete path to robust tests of subthreshold surface code scaling under biased, non-Markovian noise.