Integrated superconducting quantum computing stack designed for fault tolerance

To realise the promise of fault-tolerant quantum computing, the full quantum computing stack needs to be designed with Quantum Error Correction (QEC) in mind. Firstly, this necessitates a Quantum Processing Unit (QPU) with the right level of connectivity, operation fidelities, and the ability to rapidly and repeatedly measure the QEC parity-checks. Secondly, a scalable control system is needed that has the ability to distribute the collected measurements from multiple peripherals to a central location for processing, as well as a low-latency feedback capability to adjust the executed circuit in real-time. Finally, a real-time QEC stack needs to be able to process the received data, compute the logical state of the qubits and share that information with the control system via a low-latency link. Here, we demonstrate all of these components working together: an IQM square-grid superconducting QPU, Zurich Instruments' Quantum Computing Control System with a low-latency star-network architecture, and Riverlane QEC stack "Deltaflow 2". We will present the system architecture, individual components and interfaces, and share the results of running the QEC primitives and associated system metrics. Finally, we will discuss how the joint system can be scaled to realise fault-tolerant quantum computing.