Superconducting Qubit Gate Design Tailored for Quantum Error Correction

Quantum error correction (QEC) is one of the crucial building blocks for developing quantum computers that have significant potential for reaching a quantum advantage in applications. Prominent candidates for QEC are stabilizer codes for which periodic readout of stabilizer operators is typically implemented via successive two-qubit entangling gates and is repeated many times during a computation. Implementing such protocols imposes specific requirements on the underlying hardware. To improve QEC protocols, the physical qubits and the gates should be tailored to the needs of the QEC algorithm itself. In our work, we design superconducting circuit hardware and gate operations that are specifically optimized for QEC, focusing on understanding and reducing uncorrectable errors that limit fault-tolerant performance. By analyzing the dominant error mechanisms and refining gate implementations accordingly, we aim to realize hardware that is intrinsically aligned with the requirements of quantum error correction.