Static and Dynamic Simulations of Shuttling for FDX-22 and SiGe quantum devices
ORAL
Abstract
As quantum computing architectures approach scalability, the ability to coherently shuttle quantum states across large arrays of quantum dots (QD) becomes essential [1,2]. In particular, spin-based silicon quantum processors require reliable, low-decoherence shuttling to enable long-range interactions and flexible qubit connectivity. This work presents a comprehensive, physics-informed algorithm for optimising bias waveforms in conveyor-mode electron shuttling in linear QD arrays. The algorithm uses self-consistent Poisson–Schrödinger solvers to maintain a constant ground state energy during transport, preserving coherence and minimising motional excitation. A key innovation is the generation of time-dependent voltage sequences that yield near-constant shuttling velocity, informed by the spatial evolution of quantum states and gate lever-arms.
The method includes a robust DC bias optimisation to prevent excessive heating and to ensure formation of large, movable QDs without decoherence-inducing potential barriers using QTCAD[3]. The approach is validated across multiple platforms, including FD-SOI, SiMOS and SiGe, revealing how gate geometry, material interfaces, and layout constraints impact transport stability. In FD-SOI systems, interface-induced potential barriers introduce scattering effects that degrade performance. In contrast, SiMOS and SiGe devices with finely tuned gate geometries exhibit smoother QD motion and more uniform energy landscapes. The study highlights practical limits of conveyor-mode transport in current technologies and offers concrete guidelines for future device engineering to support scalable, high-fidelity shuttling. The FD-SOI and SiGe models are experimentally verified.
We also include the impact of valley splitting on shuttling using the QTCAD Atom package. The atomistic structure of the Si/SiGe rough interfaces was relaxed using the Keating valence force-field model. The Tight-Binding model finds the valley splitting for every position of the QD during shuttling. We also discuss the Split-operator method [4] to verify obtained results and to estimate the limited shuttling speed for a given device geometry.
[1] DOI: 10.1038/s41467-024-49182-4 [2] arXiv: 2406.07267v1 [3] DOI: 10.1063/5.0097202 [4] DOI: 10.1007/978-3-030-50433-5_50
The method includes a robust DC bias optimisation to prevent excessive heating and to ensure formation of large, movable QDs without decoherence-inducing potential barriers using QTCAD[3]. The approach is validated across multiple platforms, including FD-SOI, SiMOS and SiGe, revealing how gate geometry, material interfaces, and layout constraints impact transport stability. In FD-SOI systems, interface-induced potential barriers introduce scattering effects that degrade performance. In contrast, SiMOS and SiGe devices with finely tuned gate geometries exhibit smoother QD motion and more uniform energy landscapes. The study highlights practical limits of conveyor-mode transport in current technologies and offers concrete guidelines for future device engineering to support scalable, high-fidelity shuttling. The FD-SOI and SiGe models are experimentally verified.
We also include the impact of valley splitting on shuttling using the QTCAD Atom package. The atomistic structure of the Si/SiGe rough interfaces was relaxed using the Keating valence force-field model. The Tight-Binding model finds the valley splitting for every position of the QD during shuttling. We also discuss the Split-operator method [4] to verify obtained results and to estimate the limited shuttling speed for a given device geometry.
[1] DOI: 10.1038/s41467-024-49182-4 [2] arXiv: 2406.07267v1 [3] DOI: 10.1063/5.0097202 [4] DOI: 10.1007/978-3-030-50433-5_50
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Publication: https://arxiv.org/abs/2510.06943
Presenters
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Conor Power
- University College Dublin