Impact of Device Imperfections on Charge Transport and Valley Excitations During Electron Shuttling in SiMOS

There have been extensive theoretical studies and high-fidelity experimental demonstrations of shuttling in Si/SiGe^_1,2, but considerably less work has been done on this topic in Si/SiO₂. To address this, we build on previous 2D simulation work^₃, by performing full 3D modelling of conveyor-mode charge shuttling in realistic Si/SiO₂ devices with charged defects, gate imperfections, and roughness at the oxide interface. Using solutions to the Poisson and time-dependent Schrödinger equations for different shuttling speeds and gate voltages, we find that positive defects directly in the shuttling path capture passing electrons when using lower clavier gate voltages of 250mV. Increasing the conveyor confinement with gate voltages of 500mV ensures the passing electrons escape the trap, but they emerge in an orbitally excited state potentially opening spin-flip pathways via spin-orbit coupling and phonon relaxation. On the other hand, single negative defects don’t disrupt transport by knocking electrons into adjacent minima, but do induce orbital excitation for lower clavier gate voltages. These excitations are suppressed by increasing the confinement, and so are not expected to present an obstacle to charge shuttling. Our simulations also show charge shuttling remains robust against 30% variations in clavier gate footprint and interface roughness as high as rms=0.9nm. However, when we use these modelling tools to compute the valley splitting and phase for different interfaces, we find that even modest roughness creates adversarial valley landscapes with low splitting and rapidly changing phase. We observe that the electron is highly susceptible to valley excitations when shuttling across these interfaces for even slow shuttling speeds, which may lead to spin-dephasing and leakage out of the computational subspace. This highlights the importance of mitigation strategies currently being explored in the Si/SiGe literature to Si/SiO₂ devices, for example using variable shuttling speeds and paths or compensating for channel-specific dephasing with Z-rotations^₄.

[1] Langrock et al. (2023)

[2] De Smet et al. (2025)

[3] Jeon et al. (2025)

[4] Oda et al. (2024)