Scalable Integrated Readout for Semiconductor Quantum Dots Using Current-Biasing

Universal quantum computing requires a scalable system comprising millions of qubits. One of the current bottlenecks is achieving a fast and high fidelity readout without limiting scalability due to area consumption, wiring or power dissipation, all of which remain significant challenges. To address this issue, we have implemented cryogenic integrated circuitry using 22 nm FD-SOI technology. In its current form, the circuit interfaces with three SETs to act as a charge sensor for semiconductor quantum dots. The SETs are in a current-biasing configuration. The output voltage of all SETs is sampled simultaneously. These voltages are then digitized using time-division multiplexing (TDM). This is achieved by assigning two sample and hold (S/H) capacitors to each SET, which also enables noise reduction using correlated double sampling (CDS). This enables TDM to extend beyond the coherence time of the qubit and is only limited by the reduced amplitude resulting from charge redistribution between the S/H capacitors, as well as the parasitic wiring capacitances and the input capacitance of the readout amplifier. Adding additional SETs only requires additional S/H circuits with digital control; no active analogue parts are needed. We measure the IC at 8 K using an AWG to emulate a SET. This exhibits input-referred noise of 120 µVRMS (with a sampling time of 2 x 0.5 µs). Assuming a typical SET amplitude of 1 mV, this enables fast, high-fidelity readout with low power consumption of 121 µW. Extrapolating this for 1000 SETs gives a power consumption of 0.121 µW per SET. This paves the way for a scalable readout solution for future universal quantum computing applications.