System Integration of a Quantum System-on-a-Chip (QSoC) Controller with a 6-Qubit QPU in Silicon
ORAL
Abstract
Silicon spin qubits offer a promising route towards scalable Quantum Processor Units (QPUs) capable of real quantum advantage. Scaling remains challenging, requiring integration of high-fidelity qubits with dense classical control electronics in a precisely managed cryogenic environment. We present the co-design and integration of our Alpha5 22FDX controller chip with a 6-qubit linear-array QPU in a Si/SiGe heterostructure, demonstrating performance and scalability. Our solution addresses key challenges including co-integration, packaging, and management of parasitics, noise, and thermal effects for optimal performance.
The Alpha5 controller features a programmable pattern generator and embedded ARM core for complex plunger, barrier, and readout operations with 300 µV precision, sub-nanosecond synchronization, and an integrated CTIA readout chain resolving 1 nA currents with 10 dB SNR in <1 µs.
A modified 6-qubit Si/SiGe QPU enables DC current readout of its charge sensors in transport mode. Co-location with Alpha5 controller significantly reduces parasitics, allows MHz-band readout, and meets required benchmarks for readout speed and fidelity. An advanced gate stack is used to facilitate heterogeneous integration with the Alpha5 control chip, ensuring compatibility with industry-standard, semiconductor packaging solutions.
The controller consumes <15 mW and the QPU <60 µW, supported by our Gemini dual-head 4K/300 mK platform.
The Alpha5 controller features a programmable pattern generator and embedded ARM core for complex plunger, barrier, and readout operations with 300 µV precision, sub-nanosecond synchronization, and an integrated CTIA readout chain resolving 1 nA currents with 10 dB SNR in <1 µs.
A modified 6-qubit Si/SiGe QPU enables DC current readout of its charge sensors in transport mode. Co-location with Alpha5 controller significantly reduces parasitics, allows MHz-band readout, and meets required benchmarks for readout speed and fidelity. An advanced gate stack is used to facilitate heterogeneous integration with the Alpha5 control chip, ensuring compatibility with industry-standard, semiconductor packaging solutions.
The controller consumes <15 mW and the QPU <60 µW, supported by our Gemini dual-head 4K/300 mK platform.
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Publication: [1] Amitonov, S. et al. Spin Qubit Performance at the Error Correction Threshold... (2024).
Presenters
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David Redmond
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