Efficient Modelling of Lattice Surgery Logical Error Rates

Utility-scale quantum compilation requires choosing fault-tolerant error-correcting codes and logical operations between them in such a way that guarantees a target program execution accuracy. In the case of a surface code–based quantum computer, this amounts to predicting error rates of all lattice surgeries performed during computation.

In this work, we devise a compact and efficient framework for predicting the logical error rates of such operations in the presence of realistic hardware noise models. Our framework is based on two primitive protocols: memory, which characterizes the rate of logical error occurrence on the encoded qubits; and stability, which characterizes logical error rates associated with multi-qubit logical parity measurements conducted via lattice surgery. Using circuit-level noise simulations, we validate that these two primitives suffice for predicting the error rates of all logical operations based solely on their geometric parameters. Moreover, our techniques allow us to understand the types of errors that are dominant in the two primitives:  stability—and, by extension, multi-qubit logical parity measurement—is more sensitive to SPAM errors than memory is. Analogously, memory is more sensitive to idling noise than stability is.