Energy Efficient Tunnel Transistors Using Dielectric-Gated Band Engineered Tunnel Junctions

Low stand-by power in transistors can be improved with steep sub-threshold tunnel transistors. This work outlines the impact of band-to-band tunneling behavior in InGaAs/Ge that is modulated by HfO$_{2}$ gate on the thin InGaAs side. Numerical simulation of InGaAs/Ge Esaki tunneling heterojunction are modified with dielectric-gating to enhance electrostatic control of the junction while providing gated electrical isolation. The energy band of such structure is simulated for n-type InGaAs in conjunction with p-type germanium. Electrical and band simulation are performed for various thicknesses and doping concentrations. Peak-to-valley current ratio (PVCR) and peak current density (J$_{\mathrm{max}})$ are obtained and compared with other tunneling heterojunctions. Finally, various compositions of InGaAs, which are epitaxially compatible are simulated to maximize the PVCR and J$_{\mathrm{max}}$.