Patterning of 25-nm contact holes at 90-nm pitch: combination of L/S double exposure immersion lithography and plasma-assisted shrink technology

Extreme ultraviolet lithography (EUVL) is the leading candidates for the 16nm CMOS technology node and beyond. However, this technique still has to be improved before being able to provide enough test material for etch development. It is therefore of interest to imagine an alternative approach, allowing plasma etch scientists to study the through-node scalability of their processes. In this work, two new approaches have been combined in order to provide 25nm contact holes (CH) at 90nm pitch: the line/space (L/S) double exposure immersion lithography and the plasma-assisted shrink technology. In this paper, we will first present the line/space (L/S) imaging method with negative tone development (NTD) to create directly 45nm CH at 90nm pitch. Then, we will discuss plasma-assisted shrink technology and how it applies to these small contacts. Plasma-assisted shrink technology relies on running a fast cyclic process, where plasma polymers are deposited on the photoresist mask, then subsequently redistributed over the features sidewalls, allowing in final a diameter reduction of more than 50{\%}. The last part of this paper is devoted to the study of the scalability of advanced hard-mask-based dielectric etch, based on the above-mentioned technique.