Plasma etch reactor design challenges for high RF power applications

Plasma etching of dielectric structures of advanced semiconductor devices faces multiple challenges due to the requirements posed by scaling at advanced technology nodes. Increasing high aspect ratio of next generation memory devices requires substantial increase in ion energy and ion flux with nearly perfect plasma uniformity above the substrate. To meet these process requirements, design of small volume confined plasma reactor becomes a technical challenge. New aspects of the design, such as voltage and power management with increased applied RF powers will be discussed in this presentation.