Materials and Device Aspects of III-V 3D Transistors

Recently, III-V MOSFETs with high drain currents (I$_{ds}>$1mA/$\mu $m) and high transconductances (g$_{m}>$1mS/$\mu $m) have been achieved at sub-micron channel lengths (L$_{ch})$, thanks to the better understanding and significant improvement in high-k/III-V interfaces. However, to realize a III-V FET at beyond 14nm technology node, one major challenge is how to effectively control the short channel effects (SCE). Due to the higher permittivity and lower bandgap of the channel materials, III-V MOSFETs are more susceptible to SCE than its Si counterpart. The scaling of planar devices stops at around 150nm L$_{ch}$. The dramatic increase in DIBL beyond 150nm indicates severe impact from 2D electrostatics. Therefore, the introduction of 3-dimensonal (3D) structures to the fabrication of sub-100nm III-V FETs is necessary. In this talk, we will review the materials and device aspects of III-V 3D transistors developed very recently [1-3]. \\[4pt] [1] Y. Q. Wu \textit{et al}. IEDM Tech. Dig. 331 (2009).\\[0pt] [2] M. Radosavljevic \textit{et al.}, IEDM Tech. Dig. 126 (2010).\\[0pt] [3] J. J. Gu \textit{et al}. IEDM Tech Dig. 2011 (in press).