Die Design and Fabrication for Flip-Chip-Packaged Superconducting Quantum Processors

Quantum processors based on superconducting materials with transmon qubits present many scale-up fabrication challenges such as spurious resonances from larger cavity sizes needed to accommodate larger die sizes, tighter tolerances needed for fabrication of a multitude of coplanar waveguide (CPW) resonators coupled to individual feedlines, and excellent process control of Josephson Junction (JJ) fabrication for reliable qubit frequency targeting across large areas. Through silicon vias (TSVs) were developed for improvement of RF hygiene to eliminate spurious resonance modes that can occur due to the larger die sizes. The TSVs are superconducting, which enables the connection of the qubit ground plane to the back plane enabling improved grounding during operation in a dilution refrigerator. Superconducting circuit elements are fabricated from a NbN film chosen for its high kinetic inductance and deposited with a state-of the art tool with excellent cross-wafer uniformity. Aluminum JJs are fabricated using angled-evaporation and cross-wafer uniformity and reliability are studied. Under-bump metallization is studied for optimal assembly to a flip-chip package utilizing Indium-based ball grid array (BGA). The design and fabrication are verified on S17 and S49 quantum chips.