Utilizing 2D spin-gapless semiconductors to achieve low subthreshold slope and non-local giant magnetoresistance in FETs

The fundamental thermionic-current switching limit of conventional CMOS transistors impedes the performance improvement of CMOS technology. We propose a novel field-effect transistor (FET) concept that overcomes this limitation by utilizing type-II spin-gapless semiconductors (SGSs) as source and drain electrodes in conjunction with an intrinsic semiconductor channel material [1]. The unique electronic band structure of the SGS source-drain electrodes filters the transmission of high-energy electrons in the sub-threshold region, leading to a sub-60 mV/dec sub-threshold slope (SS) value. Additionally, the SGS electrodes give rise to a non-local giant magnetoresistance effect, enabling the proposed FET to function also as a memory element. Quantum transport simulations of the proposed FET based on two-dimensional SGS VS₂ indicate a very low SS value of 10 mV/dec, a high on/off ratio of 10⁸, and a non-local giant magnetoresistance effect of 10⁴ at room temperature. Our proposed FET combines traditional transistor functionality with energy efficiency and non-volatile memory capabilities, enabling logic-in-memory computing.