CMOS-compatible wafer-scale MOCVD of superconducting TiN in Through Silicon Vias for 3D integration of qubits

Quantum Processors with large numbers of qubits demand CMOS-compatible, superconducting Through Silicon Vias (TSV) for realizing 3D integrated architectures. The superconductor TiN is a highly suitable material for conformal coating of TSV inner side walls. So far, used processes have mostly relied on customized tools or time-consuming atomic layer deposition (ALD).

In this study, we applied a standard production tool designed for 200 mm wafers to metalize superconducting TSVs using metal-organic chemical vapor deposition (MOCVD). First, we studied the temperature dependence of the two-step cyclic process, which involves thermal deposition followed by plasma annealing, on flat Si substrates. Deposition at 570K and below is reaction-limited (ALD mode) while at higher temperatures it becomes diffusion-limited (MOCVD mode). For optimized deposition at 690 K, we achieved T_c ~ 3 K, deposition rates > 2.0 nm/cycle, resistivities < 140 µΩcm and a thickness homogeneity of 15% across the wafer. To demonstrate the successful metallization of TSV sidewalls, we used Si ring structures with an aspect ratio of 1:6. Those were electrically analyzed at room temperature as well as cryogenic temperatures proving superconductivity below 0.35 K.