3D-Integrated Superconducting Qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures

In this contribution, we present a CMOS-compatible, foundry-style fabrication process of a 24-single-qubit test-chip design, which is flip-chip bonded to a carrier chip via an indium-microbump technology, specifically developed for high frequency 3D signal routing and minimal tilt between qubit and carrier chip. Furthermore, the carrier chip technology opens a path towards large number qubit systems by the mounting of several QPUs on the same carrier.

The fabrication of qubit and carrier chips is conducted on 8” (200 mm) Si-wafers, exclusively employing established processes from the semiconductor industry and thus leveraging state-of-the-art process precision and control. The qubit chip is fabricated in an all-Al design and uses an Al/TiN/In metallization for flip-chip bonding satisfying a CMOS-compatible processing order. A newly developed bump technology on the carrier chip aims to provide minimal tilt within the chip-to-chip bonding process and uses a Nb/In metallization for superconducting connections. We furthermore present a second technology using a Nb/In stack for the bumps on both chips to further widen the range of applications of the technology.

Cryogenic measurements at ~10 mK show that the technologies enable the effective transfer of CW and pulsed microwave signals from the carrier chip to the qubits with negligible attenuation and demonstrate qubit excitation with a yield exceeding 90% in one-tone spectroscopy, underscoring the high potential of our technology.