Superconducting Through-Silicon Vias for Cryogenic Interposers using 300mm Wafer Processes

The scaling of quantum processors requires advanced packaging solutions that enable high-density, low-loss interconnects in cryogenic environments. Traditional 2D wiring approaches are increasingly constrained by routing congestion, addressability and signal integrity challenges. Superconducting through-silicon vias (TSVs) offer a scalable alternative by providing vertical interconnects and supporting 3D integration of quantum-to-classical components, reducing footprint and improving wiring density. In this talk, I will discuss the work performed at imec on developing superconducting TSVs.