Process integration of Al trilayer Josephson junction thin films in scalable superconducting qubit fabricatio

Advancements in modern semiconductor manufacturing offer the precision and control necessary to fabricate scalable, fault-tolerant quantum computing (FTQC) architectures, which require large numbers of qubits with high quality, uniformity, and reproducibility. In this work, we present a lift-off-free qubit fabrication technique—termed the Trilayer Junction (TJ) process—by using 8-inch wafer manufacturing tools and inspired by state-of-the-art production processes. This method begins with the preparation of a blanket, PVD-grown multilayer Al/AlOx/Al Josephson junction thin film, followed by industry-compatible processes such as i-line DUV lithography, hydrogen silsesquioxane (HSQ) scaffolding, anisotropic etching, and vapor hydrofluoric acid (vapor HF) etching to remove the SiOx scaffold. The TJ process preserves the integrity and quality of the trilayer Josephson junctions throughout fabrication while enabling clean scaffold removal. The approach is validated through structural inspection and Josephson junction measurements. Qubits fabricated using the TJ process demonstrate relaxation times on the order of several tens of microseconds. Our results demonstrate a viable, lift-off-free qubit fabrication route compatible with modern foundry infrastructure that minimizes damage to critical device interfaces—paving the way for scalable integration in superconducting quantum processors.