300mm fabrication of single-layer gate silicon quantum dot spin qubit devices using 0.33NA EUV lithography

Semiconductor spin qubits are promising candidates for large-scale quantum computing because of their long coherence times, high-fidelity control and similarity to standard CMOS technology, which makes them intrinsically scalable. To leverage the scalability of semiconductor spin qubits, several groups have proposed a single-layer gate architecture with back-end of line (BEOL) [1-3]. In a single-layer gate architecture, quantum dots are formed underneath plunger gates, using neighboring barrier gates to confine them and control the tunnel coupling between adjacent dots.

In this work, we show the fabrication of various single-layer gate devices, using single print 0.33NA EUV lithography for gate and BEOL patterning on 300mm wafers.

We show the fabricated trilinear array presented in ref. [3], consisting of a 2 metal-layer BEOL, as well as more compact devices that allow studying single-layer gate quantum dots at a more fundamental level: a two by two quantum dot array that can be used for transport measurements across 4 dots, and a double quantum dot device with a confinement gate and a large single-electron transistor (SET) that can be operated in a multi-electron regime to allow for precise charge sensing.



[1] Ha, Sieu D., et al. arXiv preprint arXiv:2502.08861 (2025).

[2] George, Hubert C., et al. Nano Letters 25.2): 793-799, 2024

[3] Li, R., et al. arXiv preprint arXiv:2501.17814 (2025).