300mm wafer-level characterization of quantum dots formed in industrial CMOS qubit devices

The reliable fabrication of silicon quantum dots (QDs) is a critical step toward realizing scalable quantum computing architectures. Leveraging industrial semiconductor foundries provides a promising pathway to achieve this goal, as they offer the process uniformity, precision, and scalability required for large-scale quantum device integration. However, achieving consistent charge and electronic properties across extensive QD arrays remains a major challenge.

In this work, we present 300mm wafer-level statistics of the charge properties in 2-qubit gate unit cells fabricated using an industrial CMOS Fully-Depleted Silicon-On-Insulator (FDSOI) process. The unit cell consists of a bilinear array of QDs, which through design and fabrication, is compatible with the co-integration of conventional cryogenic control and readout electronics. By measuring 1D I-V traces and 2D stability diagrams, we implement an automated characterization routine to quantify the capacitive coupling of the QDs to the various gates that make up the 2-qubit gate cell. We also demonstrate coupling between adjacent QDs and show charge detection in the few-electron regime. Our characterization workflow enables rapid screening of uniform and electrostatic defined QDs for further quantum measurements.