Probing Microscale Heat Transport Through a Silicon Substrate at Deep Cryogenic Temperatures

The drive to create utility-scale fault-tolerant quantum computers will require higher qubit densities and scalable control electronics. As many qubit platforms operate at deep-cryogenic temperatures, the use of cryo-electronics close to or even monolithically integrated with qubit chips for control functions presents a promising approach to address cryostat wiring bottlenecks. However, this introduces thermal management challenges, necessitating accurate thermal models of qubit chips. Inputs to these models include the thermal conductivities of key materials and thermal boundary resistances between chips and the thermal bath, which must be experimentally derived. 

Here, we present a novel method to extract substrate thermal conductivity and chip-to-cold-plate thermal boundary resistance as a function of temperature. We demonstrate this using a multiplexed array of thermometer diodes and on-chip heaters in a 22-nm FDSOI node. The diodes are used to extract on-chip temperature as a function of heater distance, heater power, and bath temperature from 300 mK to 4 K. Using this data, we extract the relevant thermal material properties and apply these values to a 3D FEM thermal solver to generate a thermal heatmap for arbitrary on-chip power distributions. This work paves the way for more accurate thermal models of the quantum system at deep cryogenic temperature, which in turn will help to facilitate greater qubit densities and more complex integrated cryo-CMOS.