Gate-Defined Quantum Dots and Charge Noise study of Forksheet transistors for Spin Qubit co-integration

Scalability remains one of the main challenges in developing a fault-tolerant quantum computer. A major limitation is the need for qubits to operate at deep cryogenic temperatures while being controlled and read out at room temperature, motivating the development of cryogenic CMOS electronics [1-2]. With the advent of gate-all-around transistors, the conduction channel in advanced CMOS devices is now sufficiently confined to host a quantum dot at cryogenic temperature, enabling future spin qubit operation [3-4]. This also opens the prospect of co-integrating quantum processors with their control and readout electronics within the same CMOS platform.

Here, we investigate cryogenic quantum transport in Forksheet technology developed at IMEC, a promising candidate for the next CMOS technology nodes [5]. We demonstrate improved transistor performance at 10 mK in the classical regime and observe quantum dot formation in the channel, with clear signatures of quantum transport. Charge noise measurements also reveal an average noise level at 1 Hz of 10 μV/√Hz, comparable to the low noise levels required for spin qubit operation.

[1] E. Charbon et al., in 2016 IEEE International Electron Devices Meeting (IEDM) (IEEE, San Francisco, CA, USA, 2016).

[2] M. F. Gonzalez-Zalba et al., Nat Electron 4, 872 (2021).

[3] C. Rohrbacher et al., arXiv:2312.00903 (2023).

[4] C. Rohrbacher et al., IEEE Electron Device Lett. 46, 991 (2025).

[5] H. Mertens et al., in 2021 Symposium on VLSI Technology (2021).