Fabrication and Characterization of SiMOS Shared-Gate Architecture for Surface Code Implementation

Two-dimensional quantum dot arrays are a key technology for scalable silicon-based quantum computing. One of the major challenges is the reduction of wiring complexity, for which shared-gate architectures offer a promising solution. We propose a novel shared-gate architecture based on overlapping gate processes, enabling low-noise, fine-pitch gate structures. This architecture enables key operations for quantum error correction. In our design, horizontal barrier gates are formed using first-layer confinement gates, while vertical plunger and barrier gates are defined by second- and third-layer gates. These multilayered, intersecting gates effectively reduce wiring complexity. We present the concept that this architecture supports stabilizer measurement sequences for surface code operations. To validate this, we designed and fabricated a 4x4 quantum dot array based on isotopically enriched silicon metal-oxide-semiconductor (SiMOS) technology, utilizing an industrial 300 mm wafer process. Using a portion of this device, we demonstrated key functionalities including charge sensing, formation of single and double quantum dots in both horizontal and vertical directions, and coherent spin control. We investigated the feasibility of implementing a two-qubit operation. These results clarify its advantages and the remaining challenges toward scalable silicon-based quantum computing.