Assessing Uniformity in 7x7 Quantum Dot Arrays Fabricated with CMOS Processes on 300 mm wafers

Realizing fault-tolerant quantum computers will require the integration of millions of interconnected quantum bits. Spin qubits fabricated using industrial complementary metal-oxide-semiconductor (CMOS) processes offer a promising route to monolithic integration of large qubit arrays on realistic circuit footprints. Recent advances have demonstrated qubit quality metrics beyond the threshold values required for quantum error correction. However, device-to-device variability prohibits scaling quantum processors beyond small arrays of quantum dots. In this work we assess the uniformity of relevant quantum dot metrics, including gate threshold voltages, Coulomb blockade characteristics, and charge noise. These metrics are extracted from dense 7x7 quantum dot arrays that feature parallel measurement capabilities at cryogenic temperatures. The resulting distributions, measured across length scales relevant for densely interconnected quantum processors, offer insight into variability introduced by the fabrication processes. This analysis guides future optimization strategies aimed at achieving scalable and operable quantum computing architectures.