Placing and routing quantum LDPC codes in multilayer superconducting hardware

Quantum error-correcting codes with asymptotically lower overheads than the surface code require nonlocal connectivity [1]. Leveraging multilayer routing and long-range coupling capabilities in superconducting qubit hardware, we develop Hardware-Aware Layout (HAL): a robust, runtime-efficient heuristic algorithm that automates and optimizes the placement and routing of arbitrary codes. Using HAL, we generate around 150 explicit layouts of quantum low-density parity-check (qLDPC) codes with topological structure—such as the bivariate bicycle codes [2, 3] and the open-boundary tile codes [4, 5]—and find that removing the periodic boundaries significantly lowers the hardware complexity with only a moderate reduction of logical efficiency. We also lay out highly nonlocal qLDPC code families— quantum radial [6] and Tanner codes [7]—that achieve competitive tradeoffs between hardware complexity and logical efficiency. Based on our findings, we anticipate many novel qLDPC codes to be realizable on near-term superconducting qubit hardware and inform future directions for the co-design of quantum devices and fault-tolerant architectures.

[1] S. Bravyi et al., Phys. Rev. Lett. 104, 050503 (2010).

[2] Z. Liang et al., PRX Quantum 6, 020357 (2025).

[3] S. Bravyi et al., Nature 627, 778 (2024).

[4] V. Steffan et al., arXiv:2504.09171 (2025).

[5] Z. Liang et al., arXiv:2504.08887 (2025).

[6] T. R. Scruby et al., arXiv:2406.14445 (2024).

[7] R. K. Radebold et al., arXiv:2508.05095 (2025).